Keywords : and Processing Element
International Research Journal on Advanced Science Hub,
2021, Volume 3, Issue Special Issue ICEST 1S, Pages 52-59
In Field Programmable Gate Array (FPGA) platform, Finite Impulse Response (FIR) filter is one of the important applications in the context of Digital Signal Processing (DSP). The traditional FIR is designed using a number of the adders, multipliers which enlarge the area of the filter architecture. Generally, the multiplier and adder are required to design the FIR filter. In this research, Array Multiplier (AM) is used in the Processing Element (PE) for multiply the filter inputs with coefficients. This research employs the Carry Increment Adder (CIA) in the accumulator for the adding output of the PE. The proposed method is named as AM -CIA-FIR filter. Due to the usage of AM and CIA adder, the hardware utilization of the proposed work is improved. The AM -CIA-FIR filter is implemented in Xilinx ISE software by using Verilog code on different Virtex devices in terms of Virtex-4, Virtex-5, and Virtex-6. This experiment results showed that AM -CIA-FIR filter has reduced 14.01 % of the FPGA utilization compared to the PSA-FIR filter design.