Evaluation of Bufferless Network-On-Chip with Parallel Port Allocator

Abstract

Multicore network-on-chip when scales up to hundreds of nodes, energy consumption, design complexity, and cost increases multifold owing to the structure of interconnect. Many researches are being conducted to design novel architectures to build efficient networks-on-chips. Our paper proposes an efficient bufferless design with a deflection containment technique to eliminate buffers and latency. The high cost of buffers motivates us to go for a bufferless design; however, with increasing network loads, it becomes notorious with multiple deflection and flit loss between nodes. To overcome this, we have designed a bufferless architecture with a local bypass ring within nodes to reduce deflection and packet loss. Deflection Containment with the use of local bypass ring shortens the critical path and improves performance. The architecture of our designed bufferless NoC is analyzed, and RTL implementation of its components is done with Xilinx ISE design suite, and its working is analyzed in Modelsim SE. Our evaluation proves that bufferless routing with deflection containment technique reduces power dissipation without compromising on its performance.