Efficient Low-Power SR Flip-Flop Design with On/Off Control

Abstract

Fundamental to logic circuit construction, metal oxide semiconductor (MOS) devices serve as the foundational components. The growing demands of consumers in the electronics sector are heightened by technological advancements. The utilization of nano-scale technology presents a myriad of challenges for integrated circuit (IC) designers, as no single technology comprehensively meets all requirements. The essential requirement has evolved to demand superior performance coupled with minimal power dissipation and heightened stability. Achieving low power consumption in VLSI devices is crucial for optimal efficiency. With the escalating demand for compact electronic components and devices, the electronics industry has experienced rapid growth over the past few decades. The world and technology are advancing in tandem, with an increasing demand for compact, highly efficient devices. In response to this demand, flip-flops have emerged, finding numerous applications in electronics, including their use in devices and laptops. Reducing the dimensions of flip-flops introduces challenges related to leakage current, hindering the design of low-power circuits. Addressing this issue in SR flip-flops, this paper introduces an approach referred to as OFF/ON. The realization of ONOFIC in SR flip-flops effectively mitigates leakage currents, transforming the flip-flop into a low-power consumption component.