A Modified CSD Conversion for constant multiplication architecture for Air Filter
International Research Journal on Advanced Science Hub,
2019, Volume 1, Issue 1, Pages 57-61
10.47392/irjash.2019.09
Abstract
This paper introduces an efficient hardware architecture for reconfigurable multiple constant multiplication block, based upon canonical signed digit (CSD)-based 4-bit vertical and 8-bit horizontal common sub expression elimination algorithm. The proposed architecture reduces the necessary number of full adder cells and the adder depths in addition to 4-bit specific sub-expressions (CS) in the vertical direction as well as 8-bit CSs in the horizontal direction, leading to reduces operation of adder blocks in comparison with 2-bit and 3-b binary CS elimination. In the first stage conversion of binary coefficients to canonical-signed digit reduce the adder path by lowering non-zero terms present in each coefficient. Further application of MODIFIED CSD conversion algorithm reduces the complexity in multiplicative block by identifying and eliminating the common sub expression leads to decrease in propagation delay with increase in performance of the system.[1] S. J. Darak, S. K. P. Gopi, V. A. Prasad, and E. Lai, “Low-complexity reconfigurable fast filter bank for multistandard wireless receivers,”IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 5, pp. 1202–1206, May 2014.
[2] P. K. Meher, S. Y. Park, B. K. Mohanty, K. S. Lim, and C. Yeo, “Efficient integer DCT architectures for HEVC,” IEEE Trans. Circuits Syst. Video Technol., vol. 24, no. 1, pp. 168–178, Jan. 2014.
[3] B. K. Mohanty and P. K. Meher, “Memory-efficienthigh-speed convolutionbased generic structure for multilevel 2-D DWT,” IEEETrans. Circuits Syst. Video Technol., vol. 23, no. 2, pp. 353–363,Feb. 2013.
[4] F. Feng, J. Chen, and C. H. Chang, “Hypergraph based minimum arborescence algorithm for the optimization and optimization of multiple constant multiplication,” IEEE Trans. Circuits Syst. I, Reg. Papers,vol. 63, no. 2, pp. 233–244, Feb. 2015.
[5] X. Lou, Y. J. Yu, and P. K. Meher, “Finegrained critical path analysis and optimization for area-time efficient realization of multiple constant multiplications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 3, pp. 863–872, Mar. 2015.
[6] J. W. Choi, N. Banerjee, and K. Roy, “Variation-aware low-power synthesis methodology for fixed point FIR filters,” IEEE Trans. Computer.-Aided Des. Integer. Circuits Syst., vol. 28, no. 1, pp. 87–97, Jan. 2009.
[7] J. Ding, J. Chen, and C. H. Chang, “A new paradigm of common subexpression elimination by unification of addition and subtraction,”IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 35, no. 10,pp. 1605– 1617, Oct. 2016.
[8] Y. Voronenko and M. Pushcel, “Multiplier less multiple constant multiplications,”J. ACM Trans. Algorithms, vol. 3, no. 2, May 2007,Art. no. 11.
[9] C. Y. Yao, W. C. Hsia, and Y. H. Ho, “Designing hardware efficient fixed-point FIR filter in an expanding subexpression space,” IEEE Trans.
[10] Circuits Syst., I, Reg. Papers, vol. 61, no. 1, pp. 202–212, Jan. 2014.
- Article View: 140
- PDF Download: 147