International Research Journal on Advanced Science Hub

Abstract

This paper introduces an efficient hardware architecture for reconfigurable multiple constant multiplication block, based upon canonical signed digit (CSD)-based 4-bit vertical and 8-bit horizontal common sub expression elimination algorithm. The proposed architecture reduces the necessary number of full adder cells and the adder depths in addition to 4-bit specific sub-expressions (CS) in the vertical direction as well as 8-bit CSs in the horizontal direction, leading to reduces operation of adder blocks in comparison with 2-bit and 3-b binary CS elimination. In the first stage conversion of binary coefficients to canonical-signed digit reduce the adder path by lowering non-zero terms present in each coefficient. Further application of MODIFIED CSD conversion algorithm reduces the complexity in multiplicative block by identifying and eliminating the common sub expression leads to decrease in propagation delay with increase in performance of the system.